This invention relates to improved video computer methods and apparatus, and more particularly relates to an improved circuitry for recovering stored video data bits.
In a video computer system having a RAM chip with a shift register circuit, it is conventional to employ a clock circuit to sequentially transfer data bits in the shift register to the serial output terminal of the RAM ship. A problem arises, however, from the fact that at the beginning of this transfer, the data bit which appears or is stored in the first stage of the shift register appears only at the output of the shift register. More particularly, the effect of the first clock pulse to the shift register is merely to cause the data bit at its first stage to also appear at the serial output terminal of the RAM, and it is not until the second clock pulse appears that data stored in the register begins to be recovered.
The disadvantage in the prior art systems is overcome with the present invention, however, and novel means is provided whereby the first stored data pulse in the shift register is caused to appear at both the output of the shift register andd the serial output terminal, and whereby data in the shift register can be made to appear at the serial output terminal of the RAM chip in an orderly manner.